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QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FEATURES:
* * * * * * * * * * * * *
QS5917T
5V operation 2xQ output, Q/2 output, Q output Outputs tri-state while RST low Internal loop filter RC network Low noise TTL level outputs < 500ps output skew, Q0-Q4 PLL disable feature for low frequency testing Balanced Drive Outputs 24mA 132MHz maximum frequency (2xQ output) Functional equivalent to Motorola MC88915 ESD > 2000V Latch-up > -300mA Available in QSOP and PLCC packages
DESCRIPTION
The QS5917T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: Q0-Q4, 2xQ, Q/2, Q5. Careful layout and design insures < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5917T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. In addition, TTL level outputs reduce clock signal noise. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The VCO can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5917T is designed for use in high-performance workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL
LOCK
FEEDBACK
PLL_EN
FREQ_SEL
SYNC0 SYNC1 RST
0 0 1 PHASE DETECTOR LOOP FILTER 1
VCO
1
/2
0
R Q
D
R Q
D
R Q
D
R Q
D
R Q
D
R Q
D
R Q
D Q
Q/2
Q5
Q4
Q3
Q2
Q1
Q0
2xQ
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 2000 Integrated Device Technology, Inc.
JULY 2000
DSC-5227/2
QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
GND
RST
VDD
Q5 VDD RST FEEDBACK REF_SEL SYNC0 AVDD NC AGND SYNC1 FREQ_SEL GND Q0
2 3 4 5 6 7 8 9 10 11 12 13 14
27 26 25 24 23 22 21 20 19 18 17 16 15
VDD 2xQ Q/2 GND Q3 VDD Q2 GND LOCK PLL_EN GND Q1 VDD
FEEDBACK REF_SEL SYNC0 AVDD NC AGND SYNC1 5 6 7 8 9 10 11
4
3
2
1
28
Q4
27
26 25 24 23 22 21 20 19 Q/2 GND Q3 VDD Q2 GND LOCK
12
13
14
15
16
17
18
GND
GND
Max. 6 10
VDD
FREQ_SEL
QSOP TOP VIEW
PLCC TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Max Supply Voltage to Ground DC Input Voltage VIN AC Input Voltage (pulse width 20ns) Maximum Power Dissipation (TA = 85C) TSTG Storage Temperature Range -0.5 to +7 -0.5 to +7 -3 1.2 -65 to +150
Unit V V V W C
CAPACITANCE (TA = +25C, f = 1.0MHz, VIN = 0V)
QSOP Parameter CIN COUT Typ. 3 7 Max. 4 9 Typ. 4 8 PLCC Unit pF pF
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
PLL_EN
Q0
Q1
2xQ
VDD
GND
1
28
Q4
Q5
QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Names SYNC0 SYNC1 REF_SEL FREQ_SEL FEEDBACK Q0 -Q4 Q5 2xQ Q/2 LOCK RST PLL_EN NC I/O I I I I I O O O O O I I -- Reference clock input Reference clock input Reference clock select. When 1, selects SYNC1. When 0, selects SYNC0. VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. Clock outputs Clock output. Matched in frequency, but inverted with respect to Q. Clock output. Matched in phase, but frequency is double the Q frequency. Clock output. Matched in phase, but frequency is half the Q frequency. PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to the inputs. Asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled (normal operation). PLL enable. When 1, PLL is enabled (normal operation). When 0, PLL is disabled (for testing purposes). No Connection Description
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: TA = -40C to +85C, AVDD/VDD = 5V 5%
Symbol F2XQ FQ FQ/2 Description Max Frequency, 2xQ output Max Frequency, Q0 - Q4, Q5 outputs Max Frequency, Q/2 output - 70 70 35 17.5 - 100 100 50 25 - 132 132 66 33 Units MHz MHz MHz
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QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
FREQUENCY SELECTION TABLE
SYNC (MHz) FREQ_SEL 1 1 1 1 0 0 0 0 Output Used for Feedback Q/2 Q0 -Q4 Q5 2xQ Q/2 Q0 -Q4 Q5 2xQ (allowable range) Min. Max 14 28 28 56 7 14 14 28 F2XQ / 4 F2XQ / 2 F2XQ / 2 F2XQ (1) F2XQ / 8 F2XQ / 4 F2XQ / 4 F2XQ / 2 Q/2 SYNC SYNC / 2 - SYNC / 2 SYNC / 4 SYNC SYNC / 2 - SYNC / 2 SYNC / 4 Output Frequency Relationships Q5 Q Outputs - SYNC X 2 - SYNC SYNC - SYNC / 2 - SYNC X 2 - SYNC SYNC - SYNC / 2 SYNC X 2 SYNC - SYNC SYNC / 2 SYNC X 2 SYNC - SYNC SYNC / 2 2XQ SYNC X 4 SYNC X 2 - SYNC X 2 SYNC SYNC X 4 SYNC X 2 - SYNC X 2 SYNC
NOTE: 1. For the -132 speed grade, maximum input frequency is restricted to 100MHz.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, AVDD/VDD = 5V 5%
Symbol VIH VIL VOH VOL IOZ IIN Parameter Input HIGH Voltage Level Input LOW Voltage Level Output HIGH Voltage Output LOW Voltage Output Leakage Current Input Leakage Current Test Conditions Guaranteed Logic HIGH level Guaranteed Logic LOW level VDD = Min., IOH = -24mA (1) VDD = Min., IOH = -100A VDD = Min., IOL = 24mA (1) VDD = Min., IOL = 100A VOUT = VDD or GND, VDD = Max. VIN = AVDD or GND, AVDD = Max. Min. 2 -- 2.4 3 -- -- -- -- Typ. -- -- -- -- -- -- -- -- Max. -- 0.9 -- -- 0.55 0.2 5 5 A A V Unit V V V
NOTE: 1. IOL and IOH are 12mA and -12mA, respectively, for the LOCK output.
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Input Power Supply Current per TTL Input HIGH (2) Dynamic Power Supply Current VDD = Max Test Conditions (1) VDD = Max., VIN = 3.4V Typ. 0.4 -- Max. 1.5 0.4 Unit mA mA/MHz
NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. This specification does not apply to the PLL_EN input.
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QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
INPUT TIMING REQUIREMENTS
Symbol tR, tF FI tPWC DH Description Maximum input rise and fall times, 0.8V to 2V Input Clock Frequency, SYNC0, Input clock pulse, HIGH or LOW Duty cycle, SYNC0, SYNC1 SYNC1 (1) Min. -- 14 2 25 Max. 3 F2XQ -- 75 Unit ns MHz ns %
NOTE: 1. The FI specification is based on Q output feedback. See the Frequency Selection Table for more detail on allowable SYNC input frequencies for different feedback combinations.
SWITCHING CHARACTERISTICS(1)
Symbol tSKR tSKF tSKALL tPW tPW tJ tPD tPD tLOCK tPZH tPZL tPHZ tPLZ tR, tF Output Rise/Fall Times, 0.8V to 2V 0.4 1.5 ns Output Disable Time, RST HIGH to LOW (2) 0 6 ns Parameter Output Skew Between Rising Edges, Q0-Q4 and Q/2 (1) Output Skew Between Falling Edges, Q0-Q4 (1) Output Skew, All Outputs
(1)
Min. -- -- -- TCY/2 - 0.65
(1)
Max. 350 350 500 TCY/2 + 0.65 TCY/2 + 0.5 0.25 400 400 10 7
Unit ps ps ps ns ns ns ps ps ms ns
Pulse Width, Q5, 2xQ outputs Pulse Width, Q0-Q4, Q/2 outputs Cycle-to-Cycle Jitter, 33MHz
(3)
TCY/2 - 0.5 -- - 100 - 100 -- 0
SYNC Input to Feedback Delay, 28MHz SYNC Input to Feedback Delay, 33MHz, 50 to 1.5V SYNC to Phase Lock Output Enable Time, RST LOW to HIGH (2)
NOTES: 1. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 2. Measured in open loop mode PLL_EN = 0. 3. Jitter is characterized using an oscilloscope. Measurement is taken one cycle after jitter. Jitter is characterized but not tested. See FREQUENCY SELECTION TABLE for information on proper FREQ_SEL level for specified input frequencies.
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QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
TEST LOAD
VDD
160
300 7.0V OUTPUT 20pF
OUTPUT
68
30pF
300
TEST CIRCUIT 1
TEST CIRCUIT 2
TEST CIRCUIT 2 is used for output enable/disable parameters. TEST CIRCUIT 1 is used for all other timing parameters.
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5917T provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency multiplying or inversion is performed by digital logic following the PLL (see the block diagram). The key advantage of the PLL circuit is to provide an effective zero propagation delay between the output and input signals. In fact, adding delay circuits in the feedback path, `propagation delay' can even be negative! A simplified schematic of the QS5917T PLL circuit is shown below.
SIMPLIFIED DIAGRAM OF QS5917T FEEDBACK
2xQ
Q
Q
Q/2
INPUT PHASE DETECTOR
VCO
/2
/2
The phase difference between the output and the input frequencies feeds the VCO which drives the outputs. Whichever output is fed back, it will stabilize at the same frequency as the input. Hence, this is a true negative feedback closed loop system. In most applications, the output will optimally have zero phase shift with respect to the input. In fact, the internal loop filter on the QS5917T typically provides within 150ps of phase shift between input and output.
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If the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. The respective output used for feedback will be advanced by the amount of delay in the feedback path. All other outputs will retain their proper relationships to that output.
QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
QS XXXX Device Type XX Speed X Package X Process
Blank
Industrial (-40C to +85C)
Q J
Quarter Size Outline Package Plastic Leaded Chip Carrier
-70T -100T -132T 5917T
70MHz Max. Frequency 100MHz Max. Frequency 132MHz Max. Frequency Low Skew CMOS PLL Clock Driver with Integrated Loop Filter
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